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71M6521BE
Energy Meter IC
DATA SHEET
JANUARY 2008
The AUTOWAKE and PB flag bits are shown in Table 46 because they behave similarly to interrupt flags, even though they are
not actually related to an interrupt. These bits are set by hardware when the MPU wakes from a push button or wake timeout.
The bits are reset by writing a zero. Note that the PB flag is set whenever the PB is pushed, even if the part is already awake.
Each interrupt has its own flag bit, which is set by the interrupt hardware and is reset automatically by the MPU interrupt
handler (0 through 5). XFER_BUSY has its own enable and flag bit in addition to the interrupt 6 enable and flag bit (see Table
46), and these interrupts must be cleared by the MPU software.
The external interrupts are connected as shown in Table 46. The polarity of interrupts 2 and 3 is programmable in the MPU via
the I3FR and I2FR bits in T2CON . Interrupts 2 and 3 should be programmed for falling sensitivity. The generic 8051 MPU
literature states that interrupts 4 through 6 are defined as rising edge sensitive. Thus, the hardware signals attached to
interrupts 5 and 6 are inverted to achieve the edge polarity shown in Table 46.
SFR (special function register) enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has
its own flag bit that is set by the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5).
Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in Table 47.
Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit in the
special function register IP0 and one in IP1 . If requests of the same priority level are received simultaneously, an internal
polling sequence as per Table 51 determines which request is serviced first.
An overview of the interrupt structure is given in Figure 6.
Group
0
External interrupt 0
Serial channel 1 interrupt
1
2
3
4
5
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial channel 0 interrupt
-
-
-
-
-
-
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
Table 47: Priority Level Groups
IEN enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own flag bit that is set by
the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5). XFER_BUSY has its own enable
and flag bit in addition to the interrupt 6 enable and flag bit (see Table 46) and this interrupt must be cleared by the MPU
software.
Interrupt Priority 0 Register ( IP0 )
MSB
LSB
--
WDTS
IP0.5
IP0.4
IP0.3
IP0.2
IP0.1
IP0.0
Table 48: The IP0 Register
Note: WDTS is not used for interrupt controls
Interrupt Priority 1 Register ( IP1 )
MSB
LSB
-
-
IP1.5
IP1.4
IP1.3
IP1.2
IP1.1
IP1.0
Table 49: The IP1 Register:
Page: 34 of 97
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